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1. Which of the following is the 16bit registors in 8085 processor
2. Which of the following depends on the Microprocessor ECE speed
3. In 8088, which of the following option differs from 8086
4. In 8255, ______number of modes of I/O mode of operation we have, which of the following features comes under which mode (i) A 5 bit control port is available. (ii) 3 I/O lines are available at Port C
5. In ADC 0808, which of the following pin enables high output
6. In 8279 status word, when data is read then which of the following pins are set to low, & in write to the display RAM then which of the following pins are set to low
7. Normally 8279 provides a maximum of _____ seven segment display interface with CPU
8. When 8086 Microprocessor ECE is interfaced to 8253 a programmable interval timer. Then the maximum number by which the clock frequency on one of the timers is divided by ____
9. When 8086 is interfaced to two 8259s (Programmable interrupt controllers) & 8259â€™s are in master slave configuration then the number of interrupts available to the 8086 Microprocessor ECE are ______
10. In which of the following T-state does the CPU sends the address to memory or I/O & ALE signal for demultiplexing
|Online Test Name||Microprocessor|
|Exam Type||Multiple Choice Questions|
|Category||Electronics and Communication Engineering Quiz|
|Number of Questions||48 Questions|
Answer: Option D
a and b
Answer: Option C
Address Bus Width
Answer: Option A
Data width on the output
Answer: Option B
Answer: Option D