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1. The output of a JK flipflop with asynchronous preset and clear inputs is â€˜1â€™. The output can be changed to â€˜0â€™ with one of the following conditions
2. A full adder logic circuit will have
3. For which of the following purpose Karnaugh map is used
4. Which of the following is a universal logic gate?
5. How many two input AND and OR gates are required
6. For JK flip flop with J=1, K=0, the output after clock pulse will be ________
7. To construct mod 30 counter __________ number of flip-flops are required
8. For which of the following two inputs, The NOR gate output will be low
9. The number 140 in octal is equivalent to
10. __________ is known as process of entering data into a ROM
|A full adder logic circuit will have|
Answer & Explanation
Answer: Option D
A full adder circuit will add two bits and it will also accounts the carry input generated in the previous stage. Thus three inputs and two outputs (Sum and Carry) are there.
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