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1. The output of a JK flipflop with asynchronous preset and clear inputs is â€˜1â€™. The output can be changed to â€˜0â€™ with one of the following conditions
2. A full adder logic circuit will have
3. For which of the following purpose Karnaugh map is used
4. Which of the following is a universal logic gate?
5. How many two input AND and OR gates are required
6. For JK flip flop with J=1, K=0, the output after clock pulse will be ________
7. To construct mod 30 counter __________ number of flip-flops are required
8. For which of the following two inputs, The NOR gate output will be low
9. The number 140 in octal is equivalent to
10. __________ is known as process of entering data into a ROM
|The output of a JK flipflop with asynchronous preset and clear inputs is '1'. The output can be changed to '0' with one of the following conditions|
Answer & Explanation
Answer: Option C
Preset state of JK Flip-Flop =1 With J=1 K=1 and the clock next state will be complement of the present state
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