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1. The output of a JK flipflop with asynchronous preset and clear inputs is â€˜1â€™. The output can be changed to â€˜0â€™ with one of the following conditions
2. A full adder logic circuit will have
3. For which of the following purpose Karnaugh map is used
4. Which of the following is a universal logic gate?
5. How many two input AND and OR gates are required
6. For JK flip flop with J=1, K=0, the output after clock pulse will be ________
7. To construct mod 30 counter __________ number of flip-flops are required
8. For which of the following two inputs, The NOR gate output will be low
9. The number 140 in octal is equivalent to
10. __________ is known as process of entering data into a ROM- Page 4
|Online Test Name||Digital Electronics|
|Exam Type||Multiple Choice Questions|
|Category||Electronics and Communication Engineering Quiz|
|Number of Questions||44 Questions|
Answer: Option D
To realize Y = CD + EF + G Two AND gates are required (for CD & EF).
Answer: Option B
(26)10 in BCD is (00100110) BCD Add 011 to each BCD 01011001 for excess “ 3
Answer: Option A
(17)10 = (10001)2
Answer: Option A
11010 = (1 * 24) + (1 * 23) + (0 * 22) + (1 * 21) = 26
Answer: Option C
4 to 16 is answer as the line decoder has minterms are ranging from 1 to 14.